The instruction set

The instruction set

We wanted to make the Wireworld computer as simple as we could while still being able to run worthwhile programs. We therefore settled on a highly orthogonal RISC architecture. The instruction set is as follows.

MnemonicSyntaxAction
MOVMOV Rd,RsMove content of register Rs to register Rd

You may wonder how easy it can be to write a useful program using such an economical instruction set. Fortunately, some assistance is available: some of the registers behave in special ways, as described in the following table.

RegisterAction on readAction on write
R0 Returns zero Writes value to display module
R1-R52 Reads value from register Writes value to register
R53 Returns bitwise AND of R54 with NOT R53 Writes value to register
R54 Returns bitwise AND of R53 with NOT R54 Writes value to register
R55 Returns zero Writes value to register
R56 Returns value in R55 if register R56 is non-zero, and the value in R57 otherwise Writes value to register
R57 Returns zero Writes value to register
R58 Returns R58 rotated right one place Writes value to register
R59 Returns R59 rotated left one place Writes value to register
R60 Reads value from register Writes value to register
R61 Returns sum of R60 and R61 Writes value to register
R62 Reads NOT R62 Writes value to register
R63 Returns program counter value Causes branch to given target

The instructions are stored in the registers themselves: the source and destination register numbers are coded as six bits each, and stored in the two halves of a sixteen bit value. The most significant two bits in each half are set to zero.

The program counter (register R63) is incremented after each instruction is fetched, and thus the instructions that make up a program are written into consecutive registers. Each instruction cycle involves reading the source register involved in the instruction and then writing to the destination register. For efficiency, the next instruction is prefetched while the destination register is being written, and hence there is one branch delay slot.

The adder features ‘end-around carry’, which means that negative numbers are represented using ones’ complement notation rather than the more usual two’s complement.

Next: the whole computer.

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This page most recently updated Thu Aug 7 12:10:30 BST 2014
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